Altera’s latest design software release, Quartus® II software v14.1, now supports both Generation 10 devices – Arria® 10 and MAX® 10 – in a single download. The support for Arria 10 and MAX 10 devices are summarized in Table 1. Arria 10 All Arria 10 devices: GT, GX (except 10AX032 and 10AX027), and SX (except 10AS032 and 10AS027) Final pin-outs (10AX048, 10AX057, 10AX066, 10AX090, 10AX115, 10AT090, 10AT115) SoC support Digital signal processing (DSP) hardened floating-point implementation Smart voltage ID Megafunction available Early access to the Hybrid Memory Cube (HMC) intellectual property (IP) core MAX 10 Final pin-outs: 10M02 (already available: 10M04, 10M08, 10M40, and 10M50) Vertical migration support: 10M04, 10M08, 10M40, 10M50 Enhanced Flash MegaWizardTM support for new modes such as configuration flash memory (CFM) and user flash memory (UFM) New Analog Toolkit (Beta release) for evaluating analog-to-digital converter (ADC) performance and for hardware debug Power management controller reference designs Download Quartus software Productivity Advantage Multiple Design Flows for DSP Hardened Floating-Point Blocks You can harness the performance and productivity advantages of hardened floating-point blocks in Arria 10 devices. With a hardened floating-point adder and multiplier in every DSP block, Arria 10 devices deliver up to 1.5 tera floating point operations per second (TFLOPS) of performance while reducing your floating-point design resources by 80 percent compared with previous implementations. With Quartus II software v14.1, you can realize the benefits of the hardened floating-point implementation through multiple design flows that include a model-based, C-based, and RTL-based design flow: Model-based design flow with DSP Builder and MathWorks Simulink DSP Builder enables automatic high-performance push-button HDL generation of DSP algorithms directly from the Simulink environment The updated DSP builder libraries include enhanced Math.h functions and updated design examples that support DSP blocks with hardened floating-point operators C-based design flow with the Altera® SDK for OpenCLTM* The Altera SDK for OpenCL allows users to abstract away the traditional hardware FPGA development flow for a much faster and higher level software development flow. The compiler automatically optimizes the hardware implementation by taking advantage of the floating-point operators in the DSP blocks. RTL-based design flow with IP cores You can develop floating-point algorithms by instantiating Altera’s floating-point megafunctions and MegaCore® functions directly from your RTL code. A wide range of mathematical functions support the hardened floating-point implementation (e.g. add, subtract, multiply, dot product, and accumulator). The matrix multiplier megafunction and fast Fourier transform (FFT) MegaCore function also support the hardened floating-point implementation Design Entry with Hard Floating Point This video demonstration shows the design entry (via Quartus II software megafunctions) for floating-point DSP algorithms leveraging the new hard floating-point DSP blocks in Arria 10 devices. See how the floating-point megafunctions can automatically target the new Arria 10 device DSP architecture with minimal user effort.